SRAM vs DRAM in Embedded System Design
1. Static vs Dynamic Nature
SRAM (Static RAM) stores data using bistable latches and retains data as long as power is supplied.
DRAM (Dynamic RAM) stores data as charge in capacitors and requires periodic refresh cycles to retain data.
2. Performance Characteristics
SRAM is significantly faster than DRAM due to simpler access mechanisms.
DRAM requires additional circuitry for refresh and row activation, which increases access latency.
Since SRAM does not require refresh, it delivers lower and more predictable access times.
3. Power Consumption
SRAM does not require refresh, reducing dynamic power during access.
However, SRAM uses more transistors per bit, leading to higher leakage power per bit.
DRAM is more power-efficient in terms of power per bit, but refresh operations add background power overhead.
4. Transistor Count and Density
SRAM typically uses 6 transistors per bit, while DRAM uses 1 transistor and 1 capacitor per bit.
This makes SRAM less dense and limits its scalability compared to DRAM.
5. Cost Considerations
- Due to higher transistor count and lower density, SRAM is more expensive per bit than DRAM.
6. Typical Usage
DRAM is used as main memory in PCs and laptops.
SRAM is commonly used for L1/L2/L3 caches and on-chip memories.
Common DRAM types include DRAM, SDRAM, and DDR SDRAM.
SDRAM is synchronous with the clock but transfers data on one clock edge.
DDR SDRAM transfers data on both rising and falling edges, doubling throughput.
Trade-offs Between DDR Memory and SRAM
Typically in embedded systems where CPU is guaranteed to access DDR memory and SRAM transparently (without any additional latency in fetching data from DDR), we run into cases where what size of SRAM and DDR memory is necessary considering hardware and software data structures placement. Optionally CPU is supported with L1/L2 cache for data being accessed from DDR memory, hence considerations such as which data types are cache-able and non-cache-able are to be decided by system designer.
- List out all data entities which require storage in fast path (SRAM) and slow path (DDR), some entities might require storage in both SRAM and DDR memory based on access frequency (such as key data structures). In these cases, threshold based approach - where up to a certain number of entities will be placed in SRAM and overflown entities will be placed in DDR memory. This threshold based approach makes sense for init time allocations. However for dynamic memory allocations it is suggested to keep entities pool memory restricted to either SRAM or DDR. Other alternate implementations to swap entities between DDR and SRAM can be implemented based on system functionality.
- DDR memory could be divided into chunks of memory descriptors, each memory chunk can be allotted to specific pool of overflown data entities from SRAM. Other approach is to allocate memory chunk for overflown data entities and it is up to software to use this chunk as a contiguous memory chunk of specific data entities or set of heterogeneous data entities.
- Typically there are three class of memory descriptors possible with respect to data entities:
1. entities accessed by software
2. entities accessed by both software and hardware
3. entities accessed by hardware.
Moreover type of access, such as read-only, read-write, write-only have to be considered before deciding on where to place the entities. Hardware read/write entities are suggested to be in SRAM, if desired to be in DDR memory have to consider cache-able and non-cache-able data entities.
- Analyze and list data entities which are cache-safe, cache-unsafe. This helps in when to disable and for what data items we have to enable-disable CPU caching.
- Swapping-in/out key data items to SRAM from DDR can be implemented based on performance requirements, if L1/L2 cache-memory does not scale performance for all use cases.
- In most CPU designs with memory paging implementations, CPU requires virtual addresses to access DDR memory. System designers have to be cautious when swapping in/out overflown SRAM contents to DDR, often software data entities might be overflow between two physical segments or pages, whereas virtually they appear contiguous from software perspective. Hence need to take care of which addresses are being used while swapping (physical or virtual) and also data entities straddling between two physical segments.